Wrapper design for a CDMA bus in SOC

The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires on system bus which varies from 25% up to 81%, while the main disadvantage is increase of the latency of processor read and write operations. The structure of a CDMA wrapper as an interface logic between the shared bus and IP connecting to it is described. VHDL models of two wrapper types (master and slave) are developed and verified. Four different implementations of the CDMA coding technique are presented and realized in FPGA and ASIC technologies.