Extending lower-cost packaging technology into next generation signaling: Techniques and considerations

Current industry trends, combined with present cost pressures shall force signal integrity engineers to revisit traditional “rules of thumb” such that additional bandwidth can be obtained from conventional (standard) packaging materials and methodologies. In this paper, the authors assert that some current design practices prematurely cap the useful bandwidth of current technology, and unnecessarily lead designers to ask material scientists to solve our bandwidth concerns. Every facet of the electronics industry is subject to cost pressures. Opposite these financial constraints is the continuing drive to improve performance. Every new product must evaluate the business case for the use or inclusion of a new technology, more expensive component, or increase in power. The larger design community tends to move together into and out of technology “nodes” as they become more feasible and cost effective. Whether or not a particular technology is effective at meeting the design and business goals is a function of what other technologies and consequences are traded off in order to use it. This paper examines the conventional wisdom of some common practices, in light of an attempt to forego the use of advanced packaging technologies while extending the practical life of lower-cost techniques to signaling interfaces with higher frequency content.

Packaging Design within System Schedules

One of the most important phases of design is floor-planning. Quite a few of the phenomena affecting highspeed signaling can be exacerbated or abated during this stage. Floor-planning is where the “end-to-end” signaling budget is high on the considerations list along with general wire-escape requirements, pin-pin pitch, lane-lane skew, balancing, etc. Further, one must not neglect power and clock distribution and density requirements. A significant portion of signal channel budget detractors, like inter-symbol-interference (ISI), coupled noise, reflections, attenuation can be attributed to decisions made within the floor-planning phases of component placement, stack-up definition. Effort spent here can lead to a lower cost solution instead of throwing costly technology at an application suffering from insufficient floor-planning.