Positive and negative bias temperature instability on sub-nanometer eot high-K MOSFETs

For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by interface degradation, additionally to the oxide bulk trap filling which is the dominant mechanism in over 1 nm EOT devices. For NBTI, interface degradation remains as the main mechanism in sub-nano EOT devices, and additional high contribution of the high-k bulk defects can increase the degradation below 6A EOT.