An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage

A technique is described for the automatic insertion of fault models into VHDL gate models, using a specific algorithm to calculate fault coverage. This procedure does not require any modification to the structural description of a circuit using these models. Additional optimized algorithms are added to illustrate better calculation of fault coverage of a VHDL based combinational logic circuit.