A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

In this paper, a novel unified implementation of signed/unsigned multiplication is proposed using a simple sign-control unit together with a line of multiplexers. The proposed approach is demonstrated through a 0.18 ¿m CMOS implementation of a 32-bit signed/unsigned multiplier. Reported results show that the proposed unified signed/unsigned implementation is very compact with only 0.45% silicon area overhead. The critical path delay of the proposed multiplier is about 3.13 ns.