Spur-reduction techniques for PLLs using sub-sampling phase detection

In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces on-chip loop filter area and sensitivity of the VCO to pulling. The reference spur is a major issue when the bandwidth is increased, because ripples on the VCO control line undergo less filtering by the loop filter. This paper proposes design techniques based on sub-sampling phase detection to reduce the reference spur of a 2.2GHz PLL to −80dBc at a high loop-bandwidth-to-reference-frequency ratio (f
BW
/f
ref
) of 1/20.