A normally-off GaN FET with high threshold voltage uniformity using a novel piezo neutralization technique

In this paper, we successfully demonstrate a recessed gate normally-off GaN FET on a silicon substrate with high threshold voltage (V
_th
) uniformity and low on-resistance. In order to realize high V
_th
uniformity, a novel V
_th
control technique is proposed, which we call ¿piezo neutralization technique¿. This technique includes a piezo neutralization (PNT) layer formed at the bottom of the gate recess. Since the PNT layer neutralizes the polarization charges under the gate, the V
_th
comes to be independent of the gate-to-channel span. The fabricated normally-off GaN FET with PNT structure exhibits an excellent V
_th
uniformity (¿(V
_th
) = 18 mV) and a state-of-the-art combination of the specific on-resistance (R
_on
A = 500 m ¿ mm
²
) and the breakdown voltage (V
_B
> 1000 V). The normally-off GaN FETs wtih PNT structure show great promise as power devices.