Abstract:
In these two PLA configurations, adjacent precharge lines activate, and adjacent evaluation lines evaluate, to complementary logic levels. This design-for-test technique ...Show MoreMetadata
Abstract:
In these two PLA configurations, adjacent precharge lines activate, and adjacent evaluation lines evaluate, to complementary logic levels. This design-for-test technique makes it possible to use I/sub DDQ/ tests to defect all likely bridging faults-for the most part independently of the PLA's implemented function.
Published in: IEEE Design & Test of Computers ( Volume: 16, Issue: 2, April-June 1999)
DOI: 10.1109/54.765204