A micro-network on chip with 10-Gb/s transmission link

In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13 ¿m CMOS technology. The core area of this chip is 990 ¿m*1600 ¿m and the power consumption is 155 mW (60 mW for micro-switches and 95 mW for 10-Gb/s data transceiver) at 1.2 V supply voltage with 10-Gb/s transmission data rate.