1. Introduction
Test mode power can exceed the functional power specifications for several reasons cited below. This can lead to excessive IR, inductive voltage drop, and thermal problems during manufacturing test and result in lower yield.
Low Power (LP) enabling circuitry such as power-shut off (PSO), isolation gates, etc., may be disabled during manufacturing test.
In scan designs the automatic test pattern generation (ATPG) tool may use random fill techniques to set the “don't care” bits leading to about 50% activity level in the flops. This is significantly higher than the 7–10% functional activity for many LP designs
All the clocks must be active in each scan cycle and since the clocks may have simultaneous edges there can be a significant increase in instantaneous power.
ATPG compaction algorithms maximize the faults detected in each vector. This will typically increase logic activity.
Delay tests that utilize “Launch off capture” transition approaches can cause voltage drop due to inductive effects as two high speed clock pulses follow a quiescent period.
A larger percentage of the clock gating logic may be enabled than functionally acceptable. This will increase both the activity level of the logic driven by the flip-flops and the power consumed in the clock network which can be up to half the dynamic power.