An multi-rate LDPC decoder based on ASIP for DMB-TH

Based on ASIP (application specific instruction set processor), this paper propose a decoder architecture for LDPC (low density parity check codes) in the DMB-TH standard. The decoder use a five-stage pipeline, 32-bit RISC processor and it can supports three different code rates (0.4, 0.6 and 0.8) by only modifying the program. Based on XC4VLX150, at the max frequency of 126 MHz, the max throughput of the decoder can achieve 96 Mps for 10 TDMP-decoding Iterations. Compared with other GPP and DSP implementations, this ASIP simplify the control logical and enhance the flexibility.