Contents I. Introduction
With the present trend towards the VLSI integration of analogue systems, there is a strong need for efficient output buffers which can drive large loads. This paper focuses on applications which present a need for the settling time to be low. Fast settling characteristics of MOS amplifiers are extremely important in the design of data conversion and switched-capacitor circuits [8] [7]. In synchronous circuit operation, the amplifier output has to settle down to the final value in one clocking period. The slew-rate limited period and the small-signal settling period are the two distinct parts on which the settling response of a differential pair depends. Slewing of the circuit happens when all of the current flows though one branch of the circuit. This can happen when the differential input is a step or a pulse train [8]. Slew Rate is the maximum rate at which the capacitor charges linearly, which happens when the current flowing through the capacitance at the node reaches a maximum and becomes constant. Thus, the amplifier output voltage is changed at a rate equal to the ratio of bias current to the frequency compensation capacitor [8]. The techniques to enhance slew rate include dynamically biasing the circuit [1][3]. However, this method is bound to put the circuit under stress during transients. A more power efficient method to improve settling time is by boosting the rate of charging the output node during transients [6] [5]. Since, the output is taken on a two-stage buffer; it becomes cardinal to include a nonsaturated input stage. The corresponding amplifier response will hence not be limited by the input stage behavior [3]. Here, we propose a circuit which will eliminate slewing by combining techniques efficiently, and improve the settling time also.
