I. Introduction
Low signal charge, which results from the reduced supply voltage and small node capacitance, makes nanoscale integrated circuits extremely susceptible to single event transients (SETs) [1], [2]. SETs are primarily caused by alpha particles and cosmic neutrons, which originate from package materials and intergalactic rays, respectively. As these particles pass through the silicon substrate, they generate extra electron-hole pairs (EHP) through direct or indirect ionization [3]. The EHPs get collected by sensitive nodes (e.g., reverse biased pn-junctions) of a circuit and create a voltage transient at the node. Fig. 1 shows such an event at the slave latch in a typical master-slave D flip-flop. When the amplitude and duration of the transient is large, it alters the stored value in the latch, causing a single event upset (SEU). A SEU is also referred to as a ‘soft error’ as it does not permanently damage the device. However, soft error can lead to system malfunctions and as such, state-of-the-art microprocessors require soft error protection [4].