Physical implementation of 3D integrated solenoids within silicon substrate for hybrid IC applications

This paper presents an original concept of a 3D solenoid realized in a 300μm depth High Resistivity Silicon (HRS) substrate using the Through Silicon Via (TSV) interconnection technology. Electrical performances deduced from two-ports S-parameters are reported. A comparison is performed considering first conventional O-shaped planar BiCMOS (Al Back-end) inductor, then a CMOS (45nm node, Cu Back-end) O-shaped inductor respect to area occupation together with electrical performances. A predictive electrical model is proposed and compared to measurement results. Correlations between simulation and measurements are found satisfactory.