Aging analysis of circuit timing considering NBTI and HCI

We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects - NBTI and HCI - on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides not just the cell delay degradation, but also the degradation of the output slope. To get more accurate results, the individual workload of a gate can be considered.

I. Introduction

With the continued downscaling of feature sizes in integrated digital circuits, the variation of device parameters has become a major concern. During manufacturing, variations of process parameters are inevitable. Hence, performance parameters like power consumption or operating frequency differ from the values they were designed for. After manufacturing the circuit performance degrades over time due to several aging effects that cause a drift of device parameters. These effects must be considered during a timing analysis of an aged circuit.