1. Introduction
With the development of technology, the requirements of high-resolution analog-to-digital converters (ADCs) increase. Unlike traditional ADCs, which require high accuracy building blocks, sigma-delta ADCs uses the over-sampling technique and the noise-shaping technique trades speed for accuracy and decreases the requirement of building blocks. In this way, an operation that is relatively insensitive to imperfections of the analog circuits can be obtained at the cost of increased complexity and speed in the associated digital circuit. Consequently, this has motivated that being conceived for low-frequency, high-resolution applications like audio [1], [2]. But it is difficult to design low-power high-resolution sigma-delta ADC because of the limitation of Op GBW and driving capability in CMOS technology. An 114dB sigma-delta ADCs was designed in [3] and the power dissipation was 68mw. In [4] a kind of sigma-delta modulator was designed in CMOS technology with the power dissipation equal to , but the resolution was only 13bit. An 86dB 10.5mw modulator was designed in CMOS technology in [5]. And a 16bit 3.2mw sigma-delta modulator was designed in [6]. This paper is conceived for the design of sigma-delta ADCs for audio processing in 0.18um CMOS technology with resolution of 16 bits and power dissipation is 2.6mw, using switch-capacitance discrete-time sampling technique [7]–[8].