A 1.8V 200mW 8-bit 1GSPS CMOS A/D converter with a cascaded-folding and an interpolation

In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized pre-amplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18 mum 1-poly 5-metal CMOS technology. The active chip area is 0.72 mm
²
and it consumes about 200 mW at 1.8 V power supply. The simulated result of SNDR is 46.29 dB, when F
_in
=F
_s
/2 at F
_s
=1 GHz.