I. Introduction
Designs of portable consumer electronic devices such as mobile phones, PDAs, video games and other embedded systems are increasingly demanding low power consumption to maximize the battery life, reduce weight and improve reliability. These types of power sensitive devices are usually equipped with microprocessors as the processing elements and memories as the storage units. With current CMOS technology, a large portion of power consumption is consumed in the form of dynamic power
Leakage power becomes unneglectable in nanoscaled devices. However, leakage power optimization achieves better in low-leakage component design at the physical level, for which paper [1] can be a good reference. In this paper we mainly focus on dynamic power reduction at the system level of the offchip bus.
, which in turn is determined by the bit switching and the switched load capacitance. Since the microprocessor fetches instructions over the memory bus every clock cycle and bus lines to memory are often much longer than buses within the processor, the power consumed by the bus due to instruction fetch is significant.