1. Introduction
Interconnecting the existing components of chips and appropriate design and process technologies are the main causes of progress in SoC design. On-chip physical interconnections will present a limiting factor for performance. Synchronization of future chips with a single clock source and negligible skew are other challenges; however, they would be possible with GALS (Globally Asynchronous Locally Synchronous) paradigm. Since global control of information traffic between components is very difficult and needs to keep track of each component's states, components will initiate data transfers autonomously - according to their needs. As SoC complexity scales, capturing the system's functionality with fully deterministic operation models will become increasingly difficult. Henceforth, SoC design should separate the computation from communication, as they are orthogonal issues [2].