Magnetically-enhanced capacitively-coupled plasma etching for 300 mm wafer-scale fabrication of Cu through-silicon-vias for 3D logic integration

We aim to fill the processing gap in 300 mm wafer-scale non-Bosch TSV etch process by developing production-worthy TSV etch solutions for logic-centric 3D integration. This is based on a magnetically-enhanced capacitively-coupled plasma (CCP) etching system. Key factors in this system that contribute to the control of via features such as global sidewall tapering, local sidewall roughness, Si etch rates, mask undercutting and local bowing effects were evaluated. The etching characteristics of anisotropic vias in silicon with nominal feature sizes of, but not limited to 5 mum times 25 mum (AR ~ 5) and 1 mum times 20 mum (AR ~ 20) with minimum pitches of 5 mum and 1 mum, respectively were quantified. 3 mum times 14 mum and 5 mum times 19 mum Cu-filled TSV are demonstrated by having continuous 2kAring TEOS oxide liner/100 nm Ta(TaN) barrier/2kAring Cu seed stack enabled by TSV etch.

Introduction

Performance constraints faced by typical two-dimensional scaling of traditional CMOS devices can be removed by three-dimensional (3D) integrated circuit (IC) technology. To ensure success in establishing technology as the next scaling engine for the semiconductor industry, innovation with a route towards manufacturability is very important. 3 DIC technology has been identified to provide performance gains in applications such as CMOS image sensors, stacked memories, logic IC-memory assemblies and heterogeneous integration, ultimately leading to an advanced system on stacked chips [1]–[5].