1. INTRODUCTION
The increasing complexity of digital circuits makes their development more and more challenging and tricky. Especially the verification process becomes a crucial task. Simulations provide full access to internal signals but they can only cover short periods of real time (few milliseconds). A prototype implemented in an FPGA allows to observe the device for longer periods, but yields an extremely low visibility of internal procedures, which aggravates the debugging in the case of a malfunction. Furthermore, the pure observation does not suffice yet because the ongoing miniaturization of semiconductor structures makes digital circuits more and more error prone. As a consequence fault tolerance mechanisms are required to implement reliable systems. To verify these mechanisms, waiting for the occurrence of an actual physical fault would be impractical. Instead, a dedicated manipulation of the circuit has to be applied in order to artificially produce the desired fault. In addition to the trade-off between performance and visibility, a fault injection strategy has to find a balance between intrusiveness and reproducibility.