Addressing the gate stack challenge for high mobility InxGa1-xAs channels for NFETs

Through a detailed evaluation of various dielectrics, we address the primary challenges associated with gate stacks on high electron mobility InGaAs channels. More specifically we address key gate stack issues including a) EOT scalability for high performance and electrostatic control (this work CET ~0.78 nm) with acceptable leakage both at operating and offstate for low power (this work J
_g
~1 A/cm
²
), b) understand source and impact of charge trapping, c) thermal stability on InGaAs, and d) impact of In% on interface structure and its impact on surface channel MOSFETs.