Contents I. Introduction
The data rate of DRAM has been dramatically increased and now it reaches up to 1600 Mbps in the DDR3 system [1]. As the data rate becomes higher, signal integrity of DRAM channel limits the speed performance. Only one dual in-line memory module (DIMM) is allowed per channel at 1600 Mbps while two DIMM per channel is possible below 1600 Mbps because of signal integrity (SI) issues. Also it is generally agreed that present DDR3 channel topology is not adequate to achieve over 1600 Mbps data rate. One of critical SI issues of DDR3 system is the channel crosstalk. The crosstalk occurs at the vias, connector, and packages but mostly it comes from the microstrip line in the motherboard. Figure 1 shows channel topology of DDR3 DQ and DQS. In DIMM, the DQ and DQS signals are routed using stripline. However motherboard still adopts microstrip line for DQ and DQS because of cost. It is not reasonable to add two more layers to the motherboard just for the memory interface. Sixteen DQs and DQS/DQSB are routed in parallel which are coupled transmission line structure. Since DQ pattern is random, one DQ can have same data with others what is called even mode or different data from others what is called odd mode. The propagation velocity of even mode is different from that of odd mode in the case of microstrip line, which results in skew and timing jitter. The length of microstrip line is around 5000 mil which is around 70 % of total channel length as shown in Fig. 1. Thus the crosstalk from the motherboard trace occupies significant portion of timing budget of DDR3 system. Channel topology of DDR3 system
