Phase frequency detector of delay locked loop at high frequency

This paper present the design scheme of a phase frequency Detector (PFD) which uses Domino logic. The PFD is capable of working in gigahertz range frequency with reduced the dead zone as the reset path is increased using the inverters. The linear detection range is also increased of this PFD. In particular maximum operating frequency of PFD is discussed. The proposed PFD has simple structure with using 26 transistors. It can be operated at 1.8V supply using 0.18 micron CMOS technology. This PFD is designed for RF range Delay Locked Loop.