Process simulation of trench gate and plate and trench drain SOI nLDMOS with TCAD tools

In this paper process simulation of a novel structural Silicon On Insulator(SOI) LDMOS cell with Trench Gate and Field Plate and Trench Drain (TGFPTD) was done in a sequence of advanced SOI CMOS processes with Silvaco TCAD. The simulated results indicate that the proposed TGFPTD SOI LDMOS cell is feasible to be fabricated in advanced SOI CMOS technologies and the vertical channel length of the vertical gate nMOSFET can be reduced to about 130nm.