I. INTRODUCTION
With the increasing integration density and operation frequency of CMOS integrated circuits in the era of sub-100nm, the traditional metal wiring interconnect technology is emerging as the major bottleneck to the performance improvement of VLSI system such as System-on-Chip (SoC), System-in-Package (SiP) and Network-on-Chip (NoC) etc. This limit is due to the global interconnection delay becoming significantly larger than the gate delay. Figure. 1 shows the relationship between gate and interconnect delay under different technology [1]. It is clear from this figure that under 0.18µm technology, interconnect delay dominates the speed performance. To address this challenge, a variety of new interconnect concepts and radical solutions have been developed during the past ten years. Delay. vs. Technology Node