A reduced area 1 GSPS FFT design using MRMDF architecture for UWB communication

In this paper we present a novel technique to reduce silicon area of 128 point, 1 GSPS FFT architecture called as Mixed Radix Multi-path Delay Feedback (MRMDF) architecture proposed in [1]. The architecture has been targeted 180 nm CMOS technology for fabrication. The design is intended to comply with ECMA-368 standard, which is one of the leading MB-OFDM standards for UWB application. The major bottleneck of pipelined FFT architectures is complex multipliers. For high throughput application like UWB, parallel-pipelined architecture is the most suitable choice of design. As a result one can not share complex multipliers much and hence the silicon area becomes quite huge. The proposed technique increases the utilization factor of the elemental blocks of the complex constant multipliers proposed in [1] and hence reduces its area by quite a significant amount of 7.3% i.e. around 193k sq-micron, without any performance degradation.