Energy losses in digital CMOS integrated circuits: State-of-the-art and future trends

This paper is devoted to investigations into static and dynamic energy consumption of digital CMOS VLSI systems. The analyses are performed for currently available technologies as well as the predictive ones and cover technologies from 32 nm to 3 mum. Next, the formula that describes the ratio of static versus dynamic parts of energy consumption is proposed and further analyses for technology scaling down to 10 nm are carried out.