1. INTRODUCTION
IDDQ current testing is a powerful tool for the detection of defects in CMOS ICs. However, for present and future short channel, low threshold voltage technologies the effectiveness of testing is affected by technology scaling which leads to a remarkable increase of the intrinsic (defect-free) quiescent current (here after called background current, [1] while in parallel the defective currents are decreased [2]. The estimation is that the transistor leakage current is increased by a factor of 7.5 in every technology generation [3]. In addition, the number of transistors in a single chip is increased rapidly resulting in a further increase of and a decrease in the gap between the values of and any defective current , testing is also affected by the increased with technology evolution fluctuations in the value of the IB due to manufacturing process variations. As a result, the application of testing may either lead to reduced fault coverage or yield loss.