Introduction
While several leading companies have stepped up the production of the 45nm technology, most of them are still struggling with the issue of lowering the Vdd_min of the SRAM. Several design solutions were proposed in the conference so far [1]. The suppressed word-line (WL) scheme for a single-rail 45nm SRAM was reported [1] to address SNM issues caused by ever increasing device variations with the shrinking device size. This scheme can improve SNM, but causes an unacceptable cell current (Icell) degradation in lower VDD regime. The Icell degradation, in tum, becomes the limiter of Vdd_min. Designers would usually resort to increasing the area to maintain acceptable Icell. To avoid this issue, dual-rail SRAM designs in 65nm were also proposed [2][3][4]. Two of these [2][4] disclosed the concept of adjusting CVDD to perform read/write assist, but did not disclose the actual implementation. Only [3] reported the concept (without showing any simulated & measured data) of binary switching of the CVDD level. The CVDD is fixed at a certain voltage in normal operation mode and raised to VDD in high performance mode, as shown in Fig.1. The voltage difference between CVDD and VDD, however, will limit the Vdd_min. As CVDD-VDD becomes larger than 350 mV shown in Figure 1, the cell stability starts to suffer. Conceptual CVDD design comparisons.