I. Introduction
Hybrid nanoscale architectures are a promising alternative to end of the line CMOS. Various architectures have been proposed targeting digital and analog applications. For instance, NASICs use semiconductor nanowire grids with supporting CMOS control to implement digital microprocessors [1]; CMOL is a 3D fabric with molecular devices, CMOS and nanowire layers that may be used for reconfigurable digital logic [12] as well as analog neural network implementations [17]; Cellular Neural Networks (CNN s) and Cellular Automata have been proposed using Single Electron Transistors (SETs) [18] etc.