study of incremental step pulse programming (ISPP) and STI edge effect of BE-SONOS NAND Flash

Incremental-step-pulse programming (ISPP) is a key enabler for achieving tight VT distribution for MLC NAND Flash. The ISPP characteristics for BE-SONOS NAND Flash are studied extensively in this work. Experimentally we find that the ISPP slope is very close to 1 for BE-SONOS capacitors for a wide range of EOT and O1 variations. A theoretical model is developed to prove that ISPP slope∼1 is a universal property for any charge-trapping devices, assuming charges are fully captured. However, when the device is integrated in various STI geometries, the ISPP slope is often degraded. This is due to the STI edge effect. Non-uniform injection happens along the channel width and degrades the programming efficiency at higher VT levels. The degradation of trans-conductance (gm) and subthreshold slope (S.S) during programming validates the STI edge effect. We find that through process modifications for the STI edge, the ISPP slope can be improved.

I. Introduction

In the current floating-gate NAND Flash a key design enabler is the incremental-step pulse programming (ISPP) [1] method, which provides a tight V_T distribution control for the multi-level cell (MLC) design. For charge trapping (CT) devices, this important method has not been carefully characterized. In this report, the ISPP characteristics of BE-SONOS NAND Flash [2] devices are studied extensively.