Dual standard re-configurable hardware interleaver for turbo decoding

A very low cost re-configurable hardware interleaver for two standards, 3GPP-WCMDA and 3GPP Long Term Evolution (3GPP-LTE) is presented. The interleaver is a key component of radio communication systems. Using conventional design methods, it consumes a large part of silicon area in the design of turbo encoder and decoder. The presented hardware interleaver address generation architecture, utilizes the algorithmic level hardware simplifications to achieve very low cost solution. After doing the hardware optimizations the proposed architecture consumes only 3.1 k gates with a 256 times 8 bit memory for the fully re-configurable dual standard interleaver address generator. The interleaved address is computed every clock cycle except the case of pruning (if block size is less than the row-column matrix) in 3GPP-WCDMA. In this case one additional clock cycle is consumed for valid address generation.