A review of test techniques for RFIC’s and an application of a proposed approach in a 1.9-GHz CMOS mixer

In this paper test techniques for RFICs are presented. A Built-In Test (BIT) circuit is appiied for a 1.9-GHz double balanced Gilbert-cell CMOS active mixer. The BIT circuit operation is based on the observation that the presence of catastrophic faults, like resistive bridgings, shorts and opens, or parametric faults, result in the attenuation of the output voltage amlitude (gain reduction). The BIT circuit along with an active down-conversion mixer have been designed in a 90 nm UMC CMOS technology to evaluate the efficiency of the proposed approach and experimental results are presented.

I. Introduction

In the era of Systems-on-a-Chip (SoC) design the testing of embedded RFIC's is of great importance. As the cost of test raises to 40% of the overall production cost, researchers are looking for low cost and high efficiency test techniques for RFICs. However, this is still a major issue since the testing capability of high frequency circuits is often limited by the restricted access to individual components. Moreover, the additional testing structures make RF blocks susceptible to non-linearities, noise increase or crosstalk phenomena.