I. Introduction
As scaling approaches the physical limits of devices and fabrication technology, designers will increasingly have to consider qualitative changes. Key concerns include increasing process variations, defect rates, and infant mortality rates [1]. As VLSI scaling continues along its traditional path, we will soon be in a situation where chips will have billions of devices and thousands of defects [2]. Relaxing the requirement of 100% correctness for devices and interconnections may dramatically reduce costs of manufacturing, verification, and testing. Such a paradigm shift is in any case forced by technology scaling, which leads to more transient and permanent failures of signals, logic values, devices, and interconnections [3].