Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the low- consumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.

1. INTRODUCTION

With the evolution of microelectronics, more and more high-complexity digital systems have been designed. A common characteristic of these systems is the fact that they are battery-fed, and are conceived for different applications such as wireless communication, portable computers, aerospace (satellites, missiles, etc), aviation, automobile, medical applications, etc. Since they are battery-fed, it is desirable that the batteries have a long life span, and, therefore, power dissipation is a very important parameter in the design of such systems [1]. These systems may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). The FPGAs have become a popular means to implement digital circuits. FPGA technology has grown considerably in the past few years, generating FPGAs with up to 50 million gates, thus allowing complex digital systems to be programmed in such devices [2]. Traditionally, digital circuits are implemented with components built using CMOS technology.