3D strip meander delay line structure for multilayer LTCC-based SiP applications

Recently, the timing control of high-frequency signals is strongly demanded due to the high integration density in three-dimensional (3D) LTCC-based SiP applications. Therefore, to control the skew or timing delay, new 3D delay lines will be proposed. For frailty of the signal via, we adopt the concept of coaxial line and proposed an advanced signal via structure with quasi coaxial ground (QCOX-GND) vias. We will show the simulated results using EM and Circuit simulator.

1. Introduction

In these days, low-temperature co-fired ceramic (LTCC) technology has been widely used for System-in-Package (SiP) applications because of low loss characteristics at high frequency and high integration capability. LTCC-based SiPs can include multiple semiconductor devices and passive devices in a three-dimensional (3D) package to create highly integrated products [1]. At the same time, the timing control of high-speed clock and digital data signal interconnection lines on LTCC-based SiPs is becoming a critical part of the SiP design. Since delay lines was adopted for minimization of the timing skew in the high frequency applications, various delay structures have been proposed and implemented to provide predetermined timing delay [2]. However, no researches have yet been reported about delay line structures using multilayer LTCC substrate. Therefore, a new 3D delay line structure is strongly demanded to acquire precise timing control between the critical interconnections in multilayer LTCC-based SiP. Fig. 1. Meander delay lines. The meander delay line is used to produce the required timing delay and to control the timing skew between the clock and signal traces: (a) Meander delay line design on a mother board of a laptop computer; (b) Meander delay line designs on a mother board of a desktop computer.