Design of error-tolerant cache memory for multithreaded computing

With the trend towards nanometer billion-transistor integration, reliable computing becomes increasingly challenged by semiconductor process variations and low-level physical effects. This is particularly a problem for on-chip memory circuits. In this paper, we propose an error-tolerant memory design technique based on a unique phenomenon referred to as the inter-thread transient redundancy in multithreaded computing. A new memory microarchitecture is developed that exploits dynamic mapping strategies for compensation of unpredictable performance variations and soft errors. Trace driven simulations on the SPEC CPU2000 benchmarks show the advantages of the proposed technique for improving error tolerance in multithreaded microprocessors.

I. Introduction

Semiconductor process scaling leads to explosive silicon capacity for higher chip density, faster speed, and better opportunities of reducing power dissipation. Fueled by these technological advances, research in computer architecture has been successful to boost the microprocessor performance beyond that achievable by process scaling alone. There is a clear trend towards chip multithreaded processing [1], [2] to exploit the performance benefits rendered by future nanometer billion-transistor integration.