A 256×256 separable transform CMOS imager

This paper discusses a 256×256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and inpixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8×8 general separable 2-D convolutions as well as 16×16 block transforms.