Defect evolution and C+/F+ co-implantation in millisecond Flash annealed ultra-shallow junctions

In this paper, we investigate the evolution of extended defects during a msec Flash anneal after a PAI implant and show that during the ultra-fast temperature ramp-up and ramp-down, the basic mechanisms that control the evolution of defects are not modified with respect to the relatively slower RTA anneals. In addition, we show that junction depths below 15 nm can be achieved using a US J fabrication scheme based on the combination of impurity co-implantation with msec Flash anneal.

1. Introduction

Millisecond Flash annealing at high temperatures (up to 1300°C) is a very promising technique for the fabrication of advanced ultra-shallow source/drain junctions (USJs) for future CMOS devices, because of the great advantages in both dopant diffusion and activation. Although these advantages are clear, dopant introduction is still achieved by ion implantation, either by beamline [1], [2] or Plasma implant [3], [4]. As a consequence, implantation-induced defects are still formed, which are detrimental for device performances, due to the induced leakage currents [5].