Applications using broadband digital wireless modulation require high-resolution low-power ADC over a bandwidth of few megahertz. For a WiFi or a WiMAX standard, an ADC of ~10b resolution in 5 to 20MHz bandwidth is needed. Its sampling frequency should be in a ratio of 5x the channel bandwidth to simplify the anti-aliasing filter. In order to integrate the ADC with the digital functions in an advanced CMOS technology, compliance with the thin-oxyde voltage supply is necessary.
Abstract:
A low-power 1.2 V pipelined ADC is implemented in a 65 nm CMOS process to achieve 10b resolution at 100 MS/s based on the use of a dedicated thin-oxide high-performance a...Show MoreMetadata
Abstract:
A low-power 1.2 V pipelined ADC is implemented in a 65 nm CMOS process to achieve 10b resolution at 100 MS/s based on the use of a dedicated thin-oxide high-performance analog (HPA) MOS transistor. The pipeline ADC is composed of eight 1.5b pipelined stages followed by a 2b flash converter as the last stage. In order to optimize the power consumption, the capacitances and the bias current of each stage have been scaled down along the pipeline chain. Measurement results of this ADC revealed a SNDR of 59 dB with a power dissipation of 4.5 mW. The core occupies 0.07 mm2, and 0.1 mm2 with the reference.
Date of Conference: 03-07 February 2008
Date Added to IEEE Xplore: 09 January 2009
ISBN Information: