High Speed, Low Power Four-Quadrant CMOS Current-Mode Multiplier

In this paper a new CMOS current-mode four- quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loops is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μ𝓂 standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a -3𝒹B bandwidth of 41.8 MH𝓏 and a maximum power consumption of 0.34 𝓂W.