Wafer Level Hermetic Packaging of MOEMS Devices

Hermetic packaging is required for most of MEMS devices especially for Micro-Opto-Electro-Mechanical Systems (MOEMS) devices with billions physical contacts. Chip-level hermetic packaging is a complex and costly process which counts for over 50% of device cost and does not scale. Wafer Level Packaging (WLP) provides a scalable path to cost down and is becoming a mainstream MEMS packaging method. In this paper, a hermetic wafer level packaging method using combination of anodic and glass frit bonding for MOEMS device is reported. The micro mirror structure is made of all silicon and is fabricated atop of a CMOS substrate. The WLP method includes a bonding of a transparent substrate to a silicon interposer substrate using anodic bonding. The assembly is subsequently bonded to a released CMOS-MEMS substrate using a low-temperature (<400°C glass frit material. The development work involves fine tuning and optimizing WLP processes to achieve high yield of hermetically sealing large die size on large wafer size (8"). In summary, the presented WLP scheme provides a robust and low-cost manufacturing method for packaging monolithically integrated CMOS-MEMS micro mirror devices.