Packet Reversed Packet Combining Scheme

Packet combining scheme is a well defined simple error correction scheme with erroneous copies at the receiver. It offers higher throughput combined with ARQ protocols in networks than that of basic ARQ protocols. But packet combining scheme fails to correct errors when occur in the same bit locations of two erroneous copies. In the present work, we propose a scheme that will correct error if occurs at the same bit location of the erroneous copies. The proposed scheme when combined with ARQ protocol will offer higher throughput.

I. INTRODUCTION

Packet combining (PC) scheme for correction of bit error using two successive erroneous copies of packet was introduced by Chakraborty[1]. In the scheme two erroneous copies are XORed for locating the position of bites) in error of the packet, so that the receiver can correct the error rather than requesting transmitter to retransmit the packet. The correction process proposed is the brute force bit by bit inversion in the located bit error positions and FCS check. The scheme of Chakraborty fails: (i) when the bit error locations in both the erroneous copies are same and (ii) when multiple bit errors occur as then the application of brute force bit inversion for correcting will be huge and complex. For n bits in error , on average 2^n-1 trails of attack are required.