A Quantitative Prediction Model for Hardware/Software Partitioning

An important step in Heterogeneous System Development is Hardware/Software Partitioning. This process involves exploring a huge design space. By using profiling to select hot-spots and estimate area and delay we can prune the design space considerably. We present a Quantitative Model that makes early predictions to prune the design space and support the partitioning process. The model is based on Software Complexity Metrics, which capture important aspects of functions as control intensity, data intensity, and code size. To remedy interdependence among software metrics, we performed a Principal Component Analysis. The hardware characteristics were determined by automatically generating VHDL from C using the DWARV C-to-VHDL compiler. Linear regression on these data generated our model. The model error differs per hardware characteristic. We show that for flip-flops the mean error is 69%. In conclusion, our quantitative model makes fast and sufficiently accurate area predictions in support of early Hardware/Software Partitioning.

1. INTRODUCTION

In the last few decades computing systems have become increasingly heterogeneous. Apart from general purpose processors these systems contain such elements as ASICs, DSPs, and FPGAs. Although, these systems offer several advantages over conventional computing systems - e.g. providing application specific hardware, reconfigurability, and a wider selection of COTS components - they lack the design tools to support the development process.