MORPHEUS: Heterogeneous Reconfigurable Computing

Reconfigurable architectures and NoC (Network-on-Chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adaptivity through run-time reconfiguration, opens a new area of research by considering dynamic reconfiguration. Since software parts of an embedded system can also be included into reconfigurable hardware by integration of an IP-based microcontroller, the reconfigurable architecture provides a flexible, multi-adaptive heterogeneous platformfor HW/SW co-design. In this paper, we present the European Integrated Project MORPHEUS (IST 027342). Its goal is to develop new heterogeneous reconfigurable SoCs with various sizes of reconfiguration granularity and to provide an integrated toolset of spatial and sequential design that can be used for mapping and execution of the target applications. Additionally a NoC approach is included in order to demonstrate the mentioned benefits and scalability for actual and future SoC design. The power of this approach will be demonstrated with four applications from the industrial environment.

1. INTRODUCTION

Morpheus [1] copes with the challenges of rising complexity and the enlarging design productivity gap by developing a global solution based on a modular heterogeneous System-on-Chip platform providing the disruptive technology of dynamically reconfigurable computing including completed by a software oriented design flow and a consistent toolset (see [2]). MORPHEUS strives to establish the European foundation for a new concept of flexible “domain focused platforms”, which are positioned between general purpose flexible HW and general purpose processors, and provide breakthroughs in performance and cost-effectiveness for embedded computing systems. This three-year project will finally provide a modular silicon demonstrator in 90nm technology composed of complementary run-time reconfigurable building blocks on which four complementary test-cases will be mapped.