Introduction
Ferroelectric random access memory (FRAM) has been widely pursued for not only an embedded solution but stand-alone use due to its unique advantages such as non-volatility, low power consumption and high speed particularly in write operation [1]–[3]. We had already demonstrated highly reliable 1T1C 64 Mb FRAM cell a year ago [4]. The key technologies had been a 200 nm stacked capacitor with less-damaged ferroelectric films, novel rapid thermal annealing in process integration, and a novel 1T1C reference scheme in cell architecture (i.e. a multi-reference cell equalizing scheme). As 1T1C FRAM shrinks, the decrease of cell size is inevitable, and the scaling of the capacitor stack is required. However, when the thickness of the bottom electrode reduces, an integration-related defect (PZT-popping) appears due to lack of the diffusion-barrier property, which results in a device failure. Besides, in general, as a PZT film continues to thin down, it is difficult to obtain desirable directionality in crystallinity. In this paper, we have reduced a cell-capacitor stack by introducing a glue layer between the bottom electrode and the PZT.