Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints

In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.

I. Introduction

In Today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Placement of the analog parts is an error-prone and time-consuming process. In analog placement, parasitic mismatch induced by the layout will affect the circuit performance significantly. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. For symmetry constraint, pairs of cells are required to be placed symmetrically with respect to a horizontal or vertical axis. For common centroid constraint, devices will be split into a number of smaller sub-devices and placed in rotational symmetry about a common center point. An example is shown in Fig. 1. In Fig. 1, there is a common centroid group with two devices. Each device is divided into smaller sub-devices and layout in an interleaving manner to satisfy the common centroid requirement. Besides common centroid and symmetry, other general constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a methodology that can handle all these constraints, simultaneously. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints at the same time. Fig. 1.

Layout of a differential pair (M1 and M2). Both M1 and M2 are divided into four sub-devices.