I. Introduction
Since the term System-on-Chip (SoC) was first introduced in 1993, more and more functions have been integrated into a single chip thanks to rapid advances of process technology [1]. When designing such complex chips, one of the most time-consuming processes is often design verification. The aim of design verification is to sign off a given design in several aspects, particularly for functionality and timing. The major issue is the appropriate tradeoff between verification completeness and running time. To address this, several techniques have been proposed, which are typically classified into four categories: simulation methods, static methods, formal methods, and physical methods [2].