High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation

The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which becomes exacerbated as design complexity increases. An alternative method is static timing analysis (STA), which can drastically reduce analysis time. However, STA sacrifices accuracy for speed and often produces unrealistic results such as false paths and overly pessimistic estimates. In this paper, we propose a hybrid analysis method that can significantly reduce analysis time, while preserving accuracy, with respect to the traditional gate-level simulation. Our key idea is that a large speedup would be possible by removing those events that are repetitious and unnecessary for simulation. In particular, we focus on reducing the number of clock-related events, which account for a major portion of all the events handled by a simulator. We tested the proposed method extensively with various benchmark circuits as well as industrial designs. Our experimental results exhibit that the proposed approach accelerates the total simulation speed by two times on average, yet maintaining the accuracy acquired by the traditional gate-level simulation.

I. Introduction

Since the term System-on-Chip (SoC) was first introduced in 1993, more and more functions have been integrated into a single chip thanks to rapid advances of process technology [1]. When designing such complex chips, one of the most time-consuming processes is often design verification. The aim of design verification is to sign off a given design in several aspects, particularly for functionality and timing. The major issue is the appropriate tradeoff between verification completeness and running time. To address this, several techniques have been proposed, which are typically classified into four categories: simulation methods, static methods, formal methods, and physical methods [2].