I. Introduction
Circuits manufactured with the same fabrication process flow exhibit variation in performance due to nonuniformity in process conditions. This variation is quantified by specifying a distribution of process parameters, such as transistor channel length, width, oxide thickness, etc. This distribution can be broken down into lot-to-lot, wafer-to-wafer, die-to-die, and within-die variation. Circuit designers account for such variation through worst case analysis [1]. However, within-die variation, which characterizes parameter variation within a die (chip), is not properly accounted for by worst-case analysis, and consequently, circuits are vulnerable to yield loss due to such variation.